This chapter addresses the problem of automatically generating data converter
topologies, from algorithm descriptions to behavior building blocks, using a symbolic
synthesis methodology. The discussed approach consists of an algorithm-driven
methodology, which employs a combination of symbolic signal flow graph techniques,
to generate canonical representations for data converter algorithm descriptions, together
with pattern recognition techniques, to determine the appropriate functional building
blocks for the data converter topology. The methodology is illustrated by working
examples where VERILOG-AMS descriptions are considered at the input stage, for
algorithm specification, and at the output stage, for topology description, in both cases
the CADENCE® IC Design Environment is used for validation purposes.
Keywords: Symbolic synthesis, algorithm-driven methodology, data converters, topology generation,
algorithm descriptions, signal flow graphs, canonical representations, pattern recognition, behavior
building blocks, functional building blocks, VERILOG-AMS.