The continuous development of CMOS technology today beyond many
obstacles has been witnessed by all of us. After three decades of aggressive scaling to
ever-smaller dimensions, today, MOSFET gate lengths can be less than 22 nm. There
are many challenges and limitations at the device level. Short channel effects, such as
drain induced barrier lowering, Vth roll-off, gate induced drain leakage, static leakage,
punch through, and contact resistance, are among the major blockades for sub-22 nm
technology. Many physicists have explored this extremely small dimension device and
the effects of charge and energy quantization, and that emerged the concept of single
electron conduction. Single-electron devices were being seen as one of the finest
beyond-CMOS nanodevices reported by many researchers and ITRS. These devices
were facing many roadblocks due to their ultra-small dimensions, fabrication
viabilities, room temperature operation, CMOS compatible processes, and lack of
simulation methodology. Since the last decade, the evolution of advanced e-beam
lithography, Chemical-Mechanical polishing and deposition techniques has gained
many researchers’ attention, and the trend to explore these devices is going
continuously in an upward direction. Though it is difficult to replace CMOS
technology completely, the hybridization of these devices with CMOS is one of the
major interests shown by many research works.
Keywords: Beyond CMOS nanodevices, Coulomb Blockade (CB), Hybrid SETMOS logic, Quantum-Mechanical Tunneling (QMT), Single-Electro- -Transistor (SET), Ultra-low-power logic circuits.
