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International Journal of Sensors, Wireless Communications and Control

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ISSN (Print): 2210-3279
ISSN (Online): 2210-3287

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Research Article

Design of a Power Efficient Model of PWM Generator for Green Communication using High Performance FPGAs

Author(s): Keshav Kumar*, Amanpreet Kaur and Bishwajeet Pandey

Volume 14, Issue 1, 2024

Published on: 19 January, 2024

Page: [66 - 84] Pages: 19

DOI: 10.2174/0122103279273418231212053836

Price: $65

Abstract

Aims: This paper will focus on promoting the ideas of green communication.

Background: Pulse Width Modulation (PWM) generator is used to control the power transfer in any communication model. It is one of the most crucial parts of an electrical circuit. Our main focus in this research work is to develop an energy and power-efficient PWM generator by using Field Programmable Gate Array (FPGA) logic to elevate green communication.

Objectives: Our main focus in this research work is to develop an energy and power-efficient PWM generator by using Field Programmable Gate Array (FPGA) logic to elevate green communication.

Methods: In order to make the PWM suitable for GC, we have implemented the design on VIVADO ISE from Xilinx. The power analysis as well as resource utilization are targeted on three different FPGAs.

Results: Different IO standards of Stub Series Terminated Logic (SSTL) family are explored at different FPGA’s. Power analysis is deployed on the 7 series FPGAs of 3 different categories i.e., Spartan 7 (channel length = 28 nm), Kintex 7 (channel length = 20 nm) and ultra scale Zynq 7 (channel length = 16 nm).

Conclusion: It can be concluded from power analysis that SPARTAN-7 device is the most powerefficient and ZYNQ Ultra scale+utilizes the highest amount of power. However, KINTEX-7 Ultrascale device lies in the middle of both these devices as far as power consumption is concerned. There is a reduction of 43.07% TP consumption for SPARTAN-7 device with SSTL135 IO when equated with ZYNQ Ultra scale+ with SSTL18_I IO. Also, it can be observed from sections 5.1, 5.2 and 5.3 that there is more contribution of DP in TP consumption than SP. Hence the device utilizes additional power when it is in active state than static state. Since PWM generator is an integral part of data and wireless communication, it should require less power for proficient transmission and wellorganized green computing and communication.

Keywords: PWM generator, green computing, FPGA, SSTL IO power-efficient design, green communication, data communication.

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[1]
Narayanan G, Ranganathan VT, Zhao D, Krishnamurthy HK, Ayyanar R. Space vector based hybrid PWM techniques for reduced current ripple. IEEE Trans Ind Electron 2008; 55(4): 1614-27.
[http://dx.doi.org/10.1109/TIE.2007.907670]
[2]
Siripruchyanun M P. Wardkein A fully independently adjustable, integrable simple current controlled oscillator and derivative PWM signal generator. IEICE Trans Fundam Electron Commun Comput Sci 2003; 86(12): 3119-26.
[3]
Odavic M, Sumner M, Zanchetta P, Clare JC. Clare A theoretical analysis of the harmonic content of PWM waveforms for multiplefrequency modulators. IEEE Trans Power Electron 2010; 25(1): 131-41.
[http://dx.doi.org/10.1109/TPEL.2009.2026751]
[4]
Chow WS, Chen Y. Intended belief and actual behavior in green computing in Hong Kong. J Comput Inf Syst 2009; 50(2): 136-41.
[5]
Ahmed E, Rose J. The effect of LUT and cluster size on deepsubmicron FPGA performance and density. IEEE Transactions on Very Large Scale Integration (VLSI). Systems 2004; 12(3): 288-98.
[6]
Diao L, Tang J, Loh PC, Yin S, Wang L, Liu Z. An efficient DSP–FPGA-based implementation of hybrid PWM for electric rail traction induction motor control. IEEE Trans Power Electron 2018; 33(4): 3276-88.
[http://dx.doi.org/10.1109/TPEL.2017.2707639]
[7]
Belkheiri A, Aoughellanet S, Belkheiri M. FPGA implementation of a space vector pulse width modulation technique for a two-level in-verter. Elektrotehniski Vestnik 2018; 85(3): 77-83.
[8]
Muthukumar P, Lekshmi Kanthan PS, Baldwin Immanuel T, Eswaramoorthy K. FPGA performance optimization plan for high power conversion. Soft Computing Systems. Singapore: Springer 2018.
[http://dx.doi.org/10.1007/978-981-13-1936-5_52]
[9]
Suraj S, Soman S, Jijesh JJ. Implementation of interleaved dual boost converter utilizing FPGA for PWM. IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT). Bangalore, India. 2016.20-21 May;
[http://dx.doi.org/10.1109/RTEICT.2016.7807787]
[10]
Singh S, Kaur A, Pandey B. Energy efficient flip flop design using voltage scaling on FPGA. IEEE 6th India International Conference on Power Electronics (IICPE). Kurukshetra, India. 2014.08-10 Dec;
[http://dx.doi.org/10.1109/IICPE.2014.7115855]
[11]
Kumar K, Ahmad S, Pandey B, Pandit AK, Singh D. Power efficient frequency scaled and thermalaware control unit design on FPGA. Int J Innov Technol Explor Eng 2019; 8(9): 530-3.
[12]
Bhat D, Kaur A, Singh S. Wireless sensor network specific low power FIR filter design and implementation on FPGA. 2nd International Conference on Computing for Sustainable Global Development (INDIACom). New Delhi, India. 2015.11-13 Mar;
[13]
Pandey B, Das B, Kaur A, et al. Performance evaluation of FIR filter after implementation on different FPGA and SOC and its utilization in communication and network. Wirel Pers Commun 2017; 95(2): 375-89.
[http://dx.doi.org/10.1007/s11277-016-3898-0]
[14]
Pandey B, Jain A, Kumar A, et al. Energy efficient and highperformance FIR filter design on Spartan–6 FPGA. 3c Tecnol 2019; 8(1): 36-49.
[15]
Kumar K, Kaur A, Panda SN, Pandey B. Effect of different nano meter technology-based FPGA on energy efficient UART design. 8th International Conference on Communication Systems and Network Technologies (CSNT). Bhopal, India. 2018.24-26 Nov;
[http://dx.doi.org/10.1109/CSNT.2018.8820287]
[16]
Kumar K, Pandey B, Pandit AK, El-Ebiary YB, Mjlae SA, Bamansoor S. Design of low power transceiver on Spartan-3 and Spartan-6 FPGA. Int J Innov Technol Explor Eng 2019; 8(12): 27-30.
[17]
Kumar K, Pandey P, Mohamed RR. HSTL and HSUL I/O standard-based energy-efficient control unit circuit design on FPGA. Gyancity J Elec Comput Sci 2019; 4(2): 1-7.
[http://dx.doi.org/10.21058/gjecs.2019.42003]
[18]
Pandey B, Sharan P, Dhirani LL, Hussain DA. Role of scaling of frequency and toggle rate in POD IO standards-based energy efficient ALU design on ultra scale FPGA 10th International Conference on Computational Intelligence and Communication Networks (CICN). Esbjerg, Denmark. 2018.17-19 Aug;
[http://dx.doi.org/10.1109/CICN.2018.8864933]
[19]
Siddiquee SMT. Energy efficient instruction register for green communication. Int J Eng Adv Technol 2019; 8: 312-4.
[20]
Kumar A, Pandey B, Hussain DA, Rahman MA, Jain V, Bahanasse A. Low voltage complementary metal oxide semiconductor-based energy efficient UART design on Spartan-6 FPGA. 11th International Conference on Computational Intelligence and Communication Networks (CICN). Honolulu, HI, USA. 2019.03-04 Jan;
[http://dx.doi.org/10.1109/CICN.2019.8902356]
[21]
Goswami K, Pandey B, Kumar T, Hussain DMA. Different I/O standard and technology based thermal aware energy efficient Vedic multiplier design for green wireless communication on FPGA. Wirel Pers Commun 2017; 96(2): 3139-58.
[http://dx.doi.org/10.1007/s11277-017-4345-6]
[22]
Zarakovitis CC, Ni Q, Spiliotis J. Energy-efficient green wireless communication systems with imperfect CSI and data outage. IEEE J Sel Areas Comm 2016; 34(12): 3108-26.
[http://dx.doi.org/10.1109/JSAC.2016.2600119]
[23]
Gupta G, Kaur A, Pandey B. LVCMOS based green data flip flop design on FPGA. Ninth International Conference on Advanced Computing (ICoAC). Chennai, India. 2017.14-16 Dec;
[http://dx.doi.org/10.1109/ICoAC.2017.8441192]
[24]
Kumar K, Kaur A, Ramkumar KR. Effective data transmission with UART on Kintex-7 FPGA. 12th International Conference on Computational Intelligence and Communication Networks (CICN). Bhimtal, India. 2020.25-26 Sep;
[http://dx.doi.org/10.1109/CICN49253.2020.9242604]
[25]
Kumar K, Ramkumar KR, Kaur A, Choudhary S. A survey on hardware implementation of cryptographic algorithms using field programmable gate array. IEEE 9th International Conference on Communication Systems and Network Technologies (CSNT). Gwalior, India. 2020.10-12 April;
[http://dx.doi.org/10.1109/CSNT48778.2020.9115742]
[26]
Pandey B, Pattanaik M. Low power VLSI circuit design with efficient HDL coding. International Conference on Communication Systems and Network Technologies. Gwalior, India. 2013.06-08 April;
[http://dx.doi.org/10.1109/CSNT.2013.149]
[27]
Pandey B, Yadav J, Pattanaik M. IO standard based energy efficient ALU design and implementation on 28 nm FPGA. Annual IEEE India Conference (INDICON). Mumbai, India. 2013; pp. 13-15 Dec; 1-5.
[http://dx.doi.org/10.1109/INDCON.2013.6725996]
[28]
Gupta T, Verma G, Kaur A, Pandey B, Singh A, Kaur T. Energy efficient counter design using voltage scaling on FPGA. Fifth International Conference on Communication Systems and Network Technologies. Gwalior, India. 2015.04-06 April;
[http://dx.doi.org/10.1109/CSNT.2015.131]
[29]
Singh S, Jain A, Kaur A, Pandey B. Thermal aware low power universal asynchronous receiver transmitter design on FPGA. International Conference on Computational Intelligence and Communication Networks. Bhopal, India. 2014.14-16 Nov;
[http://dx.doi.org/10.1109/CICN.2014.198]
[30]
Pandey B, Pattanaik M. Energy efficient VLSI design and implementation on 28 nm FPGA: FPGA based energy efficient register, memory and ALU design. LAP LAMBERT Academic Publishing 2013.
[31]
Rathore PS, Chatterjee JM, Kumar A, Sujatha R. Energy-efficient cluster head selection through relay approach for WSN. J Supercomput 2021; 77(7): 7649-75.
[http://dx.doi.org/10.1007/s11227-020-03593-4]
[32]
Kumar T, Pandey B, Das T, Hussain DA. I/O standard based thermal/energy efficient green communication for Wi-Fi protected access on FPGA. 6th International Congress on Ultra Modern Telecommunications and Control Systems and Workshops (ICUMT). St. Petersburg, Russia. 2014. 06-08 Oct;
[33]
Kumar T, Pandey B, Limbu MM, Das T, Kumar A. Simulation of HSTL I/O standard-based energy efficient frame buffer for digital image processor. International Conference on Robotics and Emerging Allied Technologies in Engineering (iCREATE). Islamabad, Pakistan. 2014.22-24 April;
[34]
Khattar N, Sidhu J, Singh J. Toward energy-efficient cloud computing: A survey of dynamic power management and heuristics-based optimization techniques. J Supercomput 2019; 75(8): 4750-810.
[http://dx.doi.org/10.1007/s11227-019-02764-2]
[35]
Das T, Pandey B, Rahman MA, Kumar T. SSTL based green image ALU design on different FPGA. International Conference on Green Computing, Communication and Conservation of Energy (ICGCE). Chennai, India. 2013; pp. 12-14 Dec; 146-50.
[http://dx.doi.org/10.1109/ICGCE.2013.6823417]
[36]
Pandey B, Thind V, Sandhu SK, Walia T, Sharma S. SSTL based power efficient implementation of DES security algorithm on 28nm FPGA. Int J Security Appl 2015; 9(7): 267-74.
[http://dx.doi.org/10.14257/ijsia.2015.9.7.23]
[37]
Stub Series Terminated Logic. Available from: https://en.wikipedia.org/wiki/Stub_Series_Terminated_Logic (Accessed on: 19/1/2021).

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