Negative Bias Temperature Instability (NBTI) and Channel Hot Carrier (CHC), which is also called Hot
Carrier Injection (HCI), are the leading reliability concerns for nanoscale transistors. The de facto modeling
method to analyze CHC is based on substrate current (Isub), which becomes increasingly problematic with
technology scaling as various leakage components dominate Isub. In this work, we present a unified approach
that directly predicts the change of key transistor parameters under various process and design conditions, for
both NBTI and CHC effects. Using the general reaction-diffusion model and the concept of surface potential,
the proposed method continuously captures the performance degradation across subthreshold and strong inversion
regions. Models are comprehensively verified with an industrial 65nm technology. By benchmarking
the prediction of circuit performance degradation with measured ring oscillator data and simulations of an
amplifier, we demonstrate that the proposed method predicts the degradation very well. For 65nm technology,
NBTI is the dominant reliability concern and the impact of CHC on circuit performance is relatively small.